AMS SerDes Robustness Analysis Validation Architect
full-time•California
About this role
Are you inherently curious, hands-on, and analytical? We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of high-speed SerDes PHYs, such PCIe and USB, within our system. This role is ideal for someone who is motivated to push designs to the edge through intentional stress testing and margin-finding techniques!
You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. The role demands strong collaboration with design, architecture, and system teams to ensure the IP is designed with design for testability. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires close collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production.
BS and 20 +years of relevant industry experience
PhD in Electrical Engineering or related field with 20+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug. Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and measurement setups tailored for SerDes PHYs. Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE, etc.) Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts. Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies. Proven ability to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels. Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks. Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems. Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques. Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage. Experience providing post-silicon insights that shaped future design changes. Passion for deep debug and a “find the flaw” mentality, with an interest to explore the unexpected.
Description
You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. The role demands strong collaboration with design, architecture, and system teams to ensure the IP is designed with design for testability. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires close collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production.
Minimum Qualifications
BS and 20 +years of relevant industry experience
Preferred Qualifications
PhD in Electrical Engineering or related field with 20+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug. Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and measurement setups tailored for SerDes PHYs. Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE, etc.) Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts. Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies. Proven ability to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels. Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks. Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems. Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques. Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage. Experience providing post-silicon insights that shaped future design changes. Passion for deep debug and a “find the flaw” mentality, with an interest to explore the unexpected.
Other facts
Tech stack
SerDes Design,Validation Principles,SOC/System Integration,Stress Testing,High-Speed Serial Link Protocols,Equalization Techniques,Analog/Mixed-Signal Design,Signal Integrity,Power Integrity,Programming,Data Analysis Tools,Design-for-Validation,Fault Injection,Post-Silicon Insights,Debugging,Measurement Setups
About Apple
We’re a diverse collective of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. And the same innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it. This is where your work can make a difference in people’s lives. Including your own.
Apple is an equal opportunity employer that is committed to inclusion and diversity. Visit apple.com/careers to learn more.
Team size: 10,001+ employees
Website: http://www.apple.com/careers
LinkedIn: Visit
Industry: Computers and Electronics Manufacturing
Founding Year: 1976
What you'll do
- You will architect validation strategies focusing on uncovering weaknesses in design assumptions and stress-to-fail conditions. This role involves close collaboration with design, architecture, and system teams to validate next-generation SerDes IPs from design conception through production.
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Frequently Asked Questions
What does a AMS SerDes Robustness Analysis Validation Architect do at Apple?
As a AMS SerDes Robustness Analysis Validation Architect at Apple, you will: you will architect validation strategies focusing on uncovering weaknesses in design assumptions and stress-to-fail conditions. This role involves close collaboration with design, architecture, and system teams to validate next-generation SerDes IPs from design conception through production..
Why join Apple as a AMS SerDes Robustness Analysis Validation Architect?
Apple is a leading Computers and Electronics Manufacturing company.
Is the AMS SerDes Robustness Analysis Validation Architect position at Apple remote?
The AMS SerDes Robustness Analysis Validation Architect position at Apple is based in California, United States. Contact the company through Clera for specific work arrangement details.
How do I apply for the AMS SerDes Robustness Analysis Validation Architect position at Apple?
You can apply for the AMS SerDes Robustness Analysis Validation Architect position at Apple directly through Clera. Click the "Apply Now" button above to start your application. Clera's AI-powered platform will help match your profile with this opportunity and guide you through the application process. You can also learn more about Apple on their website.