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Senior SOC Timing Engineer
full-time•Malaysia
About this role
Job Details:
Job Description:
- As an SOC Timing engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
- Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
- Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure.
Qualifications:
Proficient in physical design industry standard EDA tools such as Primetime/PTPX, Timing Constraints development and TCL, Python.
Good knowledge of physical design and PNR flow
Should have experience in timing signoff in 10nm or lower technology
BE/MS/Phd in Electronics/Electrical Engineering with 7+ Years’ experience timing closure and signoff.
Candidate should be strong in communication, problem solving and analytical skill
Job Type:
RegularShift:
Shift 1 (Malaysia)Primary Location:
Penang 15, Penang, MalaysiaAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.What you'll do
- The Senior SOC Timing Engineer will be responsible for timing closure and signoff of FPGA/SoC and subsystem timing. The candidate will work closely with design and architecture teams for timing convergence analysis and with the physical design team for timing closure.
About Altera
Welcome to Altera, where digital transformation is at the heart of everything we do. We are a forward-thinking IT development company dedicated to helping businesses navigate and thrive in the digital age. Specializing in creating innovative solutions that drive efficiency, growth, and competitive advantage, we are your trusted partner in the journey toward digital excellence.
At Altera, we understand that the digital landscape is constantly evolving, and so are the needs of your business. Our team of expert developers, designers, and strategists works closely with you to craft tailored solutions that align with your vision and goals. From custom software development to cutting-edge web and mobile applications, we empower your business with the tools and technologies needed to stay ahead in a rapidly changing world.
Our approach is centered on collaboration and innovation. We take the time to understand your unique challenges and opportunities, delivering solutions that not only meet but exceed your expectations. With Altera, digital transformation is more than just a buzzword—it's a pathway to unlocking new possibilities and achieving sustainable success.
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Frequently Asked Questions
What does a Senior SOC Timing Engineer do at Altera?
As a Senior SOC Timing Engineer at Altera, you will: the Senior SOC Timing Engineer will be responsible for timing closure and signoff of FPGA/SoC and subsystem timing. The candidate will work closely with design and architecture teams for timing convergence analysis and with the physical design team for timing closure..
Is the Senior SOC Timing Engineer position at Altera remote?
The Senior SOC Timing Engineer position at Altera is based in Malaysia, Malaysia. Contact the company through Clera for specific work arrangement details.
How do I apply for the Senior SOC Timing Engineer position at Altera?
You can apply for the Senior SOC Timing Engineer position at Altera directly through Clera. Click the "Apply Now" button above to start your application. Clera's AI-powered platform will help match your profile with this opportunity and guide you through the application process.