A
Design Verification Engineer/Lead
full-time•Bengaluru
About this role
Job Details:
Job Description:
Altera is seeking a highly technical Senior Design Verification Engineer/Lead for the FPGA IP team. The focus of this role is to plan, build, and execute the verification of new and existing features of Altera's FPGA Interface IPs, resulting in no bugs in the final design. This role requires exceptional technical depth across advanced DV methodologies and tools, combined with strong expertise in interconnect/serial protocols like Ethernet and PCIe.
Responsibilities:
Design, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly for generation of products.
Design and implement advanced verification environments, tools, and test-plans enabling first-pass silicon success; develop sophisticated testbenches, checkers, VIPs, and complex behavioral models.
Collaborate closely with architecture, design, and software teams from initial product definition and specification reviews through implementation, bring up, and productization phases; balance complexity and ensure timely, high-quality execution.
Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics.
Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resource across teams.
Champion innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows.
Mentor and develop verification engineers; establish verification best practices and drive organizational technical excellence.
Qualifications:
B.Tech/M.Tech in Electronics Engineering or related field
10+ years of relevant experience in design verification.
Strong background in simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in System Verilog HDL and industry-standard EDA tools.
Advanced hands-on coding proficiency across System Verilog/UVM, software programming languages (C/C++/), Scripting (Shell/Python/TCL).
Excellent communication and organizational skills with a proven track record of delivering on-time, high-quality silicon and establishing technical standards.
Preferred Qualifications:
Demonstrated experience with formal verification techniques, emulation or FPGA based Verification.
Experience in Ethernet and/or PCIe protocols.
Knowledge of FPGA design flow.
Job Type:
RegularShift:
Shift 1 (India)Primary Location:
Bengaluru, Karnataka, IndiaAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.What you'll do
- The role involves planning, building, and executing the verification of FPGA Interface IPs, ensuring no bugs in the final design. Responsibilities include developing verification strategies, collaborating with teams, and driving ownership of verification components.
About Altera
Welcome to Altera, where digital transformation is at the heart of everything we do. We are a forward-thinking IT development company dedicated to helping businesses navigate and thrive in the digital age. Specializing in creating innovative solutions that drive efficiency, growth, and competitive advantage, we are your trusted partner in the journey toward digital excellence.
At Altera, we understand that the digital landscape is constantly evolving, and so are the needs of your business. Our team of expert developers, designers, and strategists works closely with you to craft tailored solutions that align with your vision and goals. From custom software development to cutting-edge web and mobile applications, we empower your business with the tools and technologies needed to stay ahead in a rapidly changing world.
Our approach is centered on collaboration and innovation. We take the time to understand your unique challenges and opportunities, delivering solutions that not only meet but exceed your expectations. With Altera, digital transformation is more than just a buzzword—it's a pathway to unlocking new possibilities and achieving sustainable success.
Ready to join Altera?
Take the next step in your career journey
Frequently Asked Questions
What does a Design Verification Engineer/Lead do at Altera?
As a Design Verification Engineer/Lead at Altera, you will: the role involves planning, building, and executing the verification of FPGA Interface IPs, ensuring no bugs in the final design. Responsibilities include developing verification strategies, collaborating with teams, and driving ownership of verification components..
Is the Design Verification Engineer/Lead position at Altera remote?
The Design Verification Engineer/Lead position at Altera is based in Bengaluru, India. Contact the company through Clera for specific work arrangement details.
How do I apply for the Design Verification Engineer/Lead position at Altera?
You can apply for the Design Verification Engineer/Lead position at Altera directly through Clera. Click the "Apply Now" button above to start your application. Clera's AI-powered platform will help match your profile with this opportunity and guide you through the application process.